1. Field of the Invention
The present invention relates to a simulation apparatus and method for simulating the operation of a semiconductor integrated circuit, such as a gate-array device.
2. Prior Art
A process of manufacturing a semiconductor integrated circuit is roughly divided into a diffusion process for forming elements, such as transistors and resistors, on a semiconductor wafer, and a wiring or metallizing process for forming a wiring pattern for connecting these elements with each other. Gate-array devices are manufactured such that a common diffusion process is employed for individual devices, and the wiring process is effected in a manner that is different from one device to another. To develop each of the gate-array devices, a mask needs to be produced for forming an intended electronic circuit of the relevant gate-array device on a semiconductor substrate. In this connection, mask-pattern information needed to produce the mask is automatically prepared by an automatic layout processing implemented by a CAD (Computer Aided Design) tool.
In recent years, the CAD tool merely capable of automatic designing is not deemed satisfactory, and there is an increasing demand for a CAD tool capable of high-quality automatic designing. In particular, the electric performance of the resulting device or product depends on whether layout designing is good or not, and therefore numerous proposals have been made for ensuring the high quality of the final product at the stage of layout designing. One of the problems that are recently deemed significant from this point of view is that of voltage drop in a power supply wiring system within a chip. This problem will be explained in more detail.
A chip of a gate-array device has an internal core area 100 in which a plurality of cell rows each consisting of a multiplicity of cells 1, 1, . . . are arranged in parallel with each other, as shown in FIG. 6. Each of the cells 1 consists of a given number of transistors, and is formed in the same pattern. Various kinds of electronic circuits constituting individual gate-array devices are provided by wiring the transistors in each of these cells 1. Power is supplied to each of the cells so that the transistors in the relevant cell constitute a desired electronic circuit. In the example of FIG. 6, relatively wide power supply wire and ground wire (not shown) are formed on the right and left sides of the internal core area 100, and power supply wires J1-Jn and ground wires K1-Kn which longitudinally extends through the respective cell rows are connected to the above power supply wire and ground wire. Power is supplied to the transistors in each cell through these power supply wires J1-Jn and ground wires K1-Kn.
The width of the power supply wires J1-Jn and ground wires K1-Kn that longitudinally extends through the cell rows cannot be increased to a great extent in view of a requirement for an increased density of integration of the chip, resulting in a relatively large resistance per unit length of the wire. FIG. 7 shows a feeder system consisting of a power supply wire JX and a ground wire KX for supplying a power supply voltage Vcc to one of the cell rows. In this figure, R represents resistance of the wiring, and IA and IB represent current that flows in accordance with the operation of each of the transistors in the cell row. The power supply wire JX and ground wire KX undergo only a slight voltage drop due to flow of the current IA since the transistors causing the flow of the current IA are located near the end of the cell row. Accordingly, the power supply voltage Vcc is applied as it is to these transistors. On the other hand, the transistors causing flow of the current IB are located in the middle of the cell row, and therefore the flow of the current IB results in a relatively large voltage drop in the power supply wire JX and ground wire KX. Accordingly, a power supply voltage that is considerably lower than the original power supply voltage Vcc is applied to these transistors.
If the power supply voltage is thus reduced at respective parts of the internal core area 1, the circuit may operate in a way different from the intended one, and, in the worst case, may not be able to fulfill the intended function. In a general method of developing individual gate-array devices, for example, an electronic circuit to be designed for each of the devices is initially subjected to logical simulation, and layout designing and following steps are then carried out after it is confirmed through the simulation that the circuit can fulfill the intended function. The logical simulation is conducted on the assumption that a given power supply voltage is uniformly applied to the entire internal core area, with the delay time being set for each element of the circuit under this assumption. If the power supply voltage applied to each part of the internal core area 1 is reduced, the assumption on which the logical simulation is effected differs from that on which operating simulation is effected, whereby the circuit operates in a different way than the intended one, e.g., with varying delay time of signal transfer in the electronic circuit. Thus the normal operation may not be reproduced in the actual operation even if the normality is confirmed by the simulation.
To avoid the above situation, layout designing should be conducted so as not to cause an undesirably large voltage drop in a particular power supply wire or wires and the like. To this end, upon completion of automatic layout, current flowing through each circuit element disposed on each cell row needs to be checked to determine a magnitude of the voltage drop in the corresponding power supply wire or the like, and another automatic layout must be effected if a large voltage drop is detected in the power supply wire or the like. In the actual application, however, it is extremely difficult to check the current in advance with respect to all circuit elements constituting a large-scale circuit, and determine or quantify the voltage drop in the power supply wiring or the like in the chip. Accordingly, the following method is actually employed to check if a circuit fails to operate properly due to any voltage drop in its power supply wiring or the like; after the automatic layout is carried out, a mask is produced on the basis of the result of the layout, to make a prototype of each of the individual gate-array devices, and this prototype is evaluated in terms of the operation to determine whether a malfunction or the like exists in the prototype due to a voltage drop in the power supply wiring or the like.